RTL clock gating uses this enable signal to control a clock gating circuit which is connected to the clock ports of all of the flip-flops with the common enable term. Traditional methodologies use this enable term to control the select on a multiplexer connected to the D port of the flip-flop or to control the clock enable pin on a flip-flop with clock enable capabilities. RTL clock gating works by identifying groups of flip-flops which share a common enable control signal. They identify the circuits where clock gating can be inserted. Automatic clock gating is supported by modern EDA tools. It is good design idea to turn off the clock when it is not needed. The components of this power are:ġ) Power consumed by combinatorial logic whose values are changing on each clock edgeģ) The power consumed by the clock buffer tree in the design. Clock tree consume more than 50 % of dynamic power.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |